Technical Field
The present invention relates generally to computing systems, and more specifically, to systems and methods for synchronizing and processing of memory access operations in such computing systems where multiple processor units and input/output units share data structures in a memory for memory-based messaging.
Description of the Related Art
In high-performance computer systems, a plurality of central processor units (CPUs) are typically operated in a parallel fashion in conjunction with other system units, including several input/output (I/O) units, by providing all system units with relatively autonomous accessibility to a common system memory (e.g., the primary or main memory). These system units are capable of both reading from and writing to locations within the main memory. Because the system units share data structures in main memory and because memory access requests originating from these units are asynchronous in nature, memory access conflicts arise when access to identical locations in memory is requested by different system units at the same time. Accordingly, access to main memory is controlled in such a manner that memory access requests are sequenced correctly so as to avoid access conflicts without paying too much overhead for the control.